vishay siliconix si8415db document number: 73210 s-82118-rev. b, 08-sep-08 www.vishay.com 1 p-channel 12-v (d-s) mosfet features ? trenchfet ? power mosfet ? micro foot ? chipscale packaging reduces footprint area profile (0.62 mm) and on-resistance per footprint area ? ultra-low on-resistance applications ? load switch, charger switch, and pa switch for portable devices product summary v ds (v) r ds(on) ( )i d (a) q g (typ.) - 12 0.037 at v gs = - 4.5 v - 7.3 19 0.046 at v gs = - 2.5 v - 6.6 0.060 at v gs = - 1.8 v - 5.8 micro foot 32 41 s dd g b u mp side v ie w backside v ie w device markin g : 8 415 xxx = date/lot tracea b ility code 8 415 xxx orderin g information: si 8 415db-t1-e1 (lead (p b )-free) s g d p-channel mosfet notes: a. surface mounted on 1" x 1" fr4 board. b. refer to ipc/jedec (j-std-020c), no manual or hand soldering. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol 5 s steady state unit drain-source voltage v ds - 12 v gate-source voltage v gs 8 continuous drain current (t j = 150 c) a t a = 25 c i d - 7.3 - 5.3 a t a = 70 c - 5.9 - 4.3 pulsed drain current i dm - 25 continuous source current (diode conduction) a i s - 2.5 - 1.3 maximum power dissipation a t a = 25 c p d 2.77 1.47 w t a = 70 c 1.77 0.94 operating junction and storage temperature range t j , t stg - 55 to 150 c package reflow conditions b ir/convection 260 thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a t 5 s r thja 35 45 c/w steady state 72 85 maximum junction-to-foot (drain) steady state r thjf 16 20 rohs compliant
www.vishay.com 2 document number: 73210 s-82118-rev. b, 08-sep-08 vishay siliconix si8415db notes: a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not subject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. typical characteristics 25 c, unless otherwise noted specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static gate threshold voltage v gs(th) v ds = v gs , i d = - 250 a - 0.4 - 1 v gate-body leakage i gss v ds = 0 v, v gs = 8 v 100 na zero gate voltage drain current i dss v ds = - 12 v, v gs = 0 v - 1 a v ds = - 12 v, v gs = 0 v, t j = 70 c - 5 on-state drain current a i d(on) v ds - 5 v, v gs = - 4.5 v - 5 a drain-source on-state resistance a r ds(on) v gs = - 4.5 v, i d = - 1 a 0.031 0.037 v gs = - 2.5 v, i d = - 1 a 0.038 0.046 v gs = - 1.8 v, i d = - 1 a 0.050 0.060 forward transconductance a g fs v ds = - 10 v, i d = - 1 a 11 s diode forward voltage a v sd i s = - 1 a, v gs = 0 v - 0.8 - 1.1 v dynamic b total gate charge q g v ds = - 6 v, v gs = - 4.5 v, i d = - 1 a 19 30 nc gate-source charge q gs 1.9 gate-drain charge q gd 4.8 gate resistance r g f = 1 mhz 19 tu r n - o n d e l ay t i m e t d(on) v dd = - 6 v, r l = 6 i d ? - 1 a, v gen = - 4.5 v, r g = 6 15 25 ns rise time t r 32 50 turn-off delay time t d(off) 180 270 fall time t f 115 175 source-drain reverse recovery time t rr i f = - 1 a, di/dt = 100 a/s 80 120 output characteristics 0 5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v gs = 5 thr u 2.5 v 2 v v ds - drain-to-so u rce v oltage ( v ) - drain c u rrent (a) i d 1 v 1.5 v transfer characteristics 0 5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 2.5 25 c t c = 125 c -55 c v gs - gate-to-so u rce v oltage ( v ) - drain c u rrent (a) i d
document number: 73210 s-82118-rev. b, 08-sep-08 www.vishay.com 3 vishay siliconix si8415db typical characteristics 25 c, unless otherwise noted on-resistance vs. drain current gate charge source-drain diode forward voltage 0.00 0.02 0.04 0.06 0.0 8 0.10 0.12 0 5 10 15 20 25 - on-resistance ( ) r ds(on) i d - drain c u rrent (a) v gs = 2.5 v v gs = 4.5 v v gs = 1. 8 v 0 1 2 3 4 5 0 5 10 15 20 25 v ds = 6 v i d = 1 a - gate-to-so u rce v oltage ( v ) q g - total gate charge (nc) v gs v sd - so u rce-to-drain v oltage ( v ) 0.0 0.2 0.4 0.6 0. 8 1.0 1.2 1.4 1.6 t j = 150 c 30 10 1 - so u rce c u rrent (a) i s t j = 25 c capacitance on-resistance vs. junction temperature on-resistance vs. gate-to-source voltage 0 500 1000 1500 2000 2500 0246 8 10 12 c rss c oss c iss v ds - drain-to-so u rce v oltage ( v ) c - capacitance (pf) 0. 8 0.9 1.0 1.1 1.2 1.3 1.4 - 50 - 25 0 25 50 75 100 125 150 v gs = 4.5 v i d = 1 a t j - j u nction temperat u re (c) r ds(on) - on-resistance ( n ormalized) 0.00 0.02 0.04 0.06 0.0 8 0.10 012345 - on-resistance ( ) r ds(on) v gs - gate-to-so u rce v oltage ( v ) i d = 1 a
www.vishay.com 4 document number: 73210 s-82118-rev. b, 08-sep-08 vishay siliconix si8415db typical characteristics 25 c, unless otherwise noted threshold voltage - 0.2 - 0.1 0.0 0.1 0.2 0.3 0.4 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a variance (v) v gs(th) t j - temperature (c) single pulse power, junction-to-ambient 0.001 0 40 8 0 60 10 time (s) 20 po w er ( w ) 0.01 0.1 1 100 600 safe operating area 100 1 0.1 1 10 100 0.01 10 t a = 25 c single p u lse - drain c u rrent (a) i d p(t) = 10 dc 0.1 i d(on) limited limited b y r ds(on) * b v dss limited p(t) = 1 p(t) = 0.1 p(t) = 0.01 p(t) = 0.001 i dm limited v ds - drain-to-so u rce v oltage ( v ) * v gs minim u m v gs at w hich r ds(on) is specified normalized thermal transient impedance, junction-to-ambient 10 -3 10 -2 0 0 6 0 1 1 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1. d u ty cycle, d = 2. per unit base = r thja = 72 c/ w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 n otes: 4. s u rface mo u nted p dm
document number: 73210 s-82118-rev. b, 08-sep-08 www.vishay.com 5 vishay siliconix si8415db typical characteristics 25 c, unless otherwise noted normalized thermal transient impedance, junction-to-foot 10 -3 10 -2 10 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1
www.vishay.com 6 document number: 73210 s-82118-rev. b, 08-sep-08 vishay siliconix si8415db package outline micro foot: 4-bump (2 x 2, 0.8 mm pitch) notes (unless otherwise specified): 1. laser mark on the silicon die back, coat ed with a thin metal. 2. bumps are 95.5/3.8/0.7 sn/ag/cu. 3. non-solder mask defined copper landing pad. 4. the flat side of wafers is oriented at the bottom. notes: a. use millimeters as the primary measurement. vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?73210 . bump note 2 8415 xxx recommended land mark on backside of die silicon b diamerter e e a a 2 a 1 e s d e s e 4 x 0.30 0.31 note 3 solder mask 0.40 dim. millimeters a inches min. max. min. max. a 0.600 0.650 0.0236 0.0256 a 1 0.260 0.290 0.0102 0.0114 a 2 0.340 0.360 0.0134 0.0142 b 0.370 0.410 0.0146 0.0161 d 1.520 1.600 0.0598 0.0630 e 1.520 1.600 0.0598 0.0630 e 0.750 0.850 0.0295 0.0335 s 0.370 0.380 0.0146 0.0150
an824 vishay siliconix document number: 71990 06-jan-03 www.vishay.com 1 pcb design and assembly guidelines for micro foot products johnson zhao introduction vishay siliconix?s micro foot product family is based on a wafer-level chip-scale packaging (wl-csp) technology that implements a solder bump process to eliminate the need for an outer package to encase the silicon die. micro foot products include power mosfets, analog switches, and power ics. for battery powered compact devices, this new packaging technology reduces board space requirements, improves thermal performance, and mitigates the parasitic effect typical of leaded packaged products. for example, the 6 ? bump micro foot si8902edb common drain power mosfet, which measures just 1.6 mm x 2.4 mm, achieves the same performance as tssop ? 8 devices in a footprint that is 80% smaller and with a 50% lower height profile (figure 1). a micro foot analog switch, the 6 ? bump dg3000db, offers low charge injection and 1.4 w on ? resistance in a footprint measuring just 1.08 mm x 1.58 mm (figure 2). vishay siliconix micro foot products can be handled with the same process techniques used for high-volume assembly of packaged surface-mount devices. with proper attention to pcb and stencil design, the device will achieve reliable performance without underfill. the advantage of the device?s small footprint and short thermal path make it an ideal option for space-constrained applications in portable devices such as battery packs, pdas, cellular phones, and notebook computers. this application note discusses the mechanical design and reliability of micro foot, and then provides guidelines for board layout, the assembly process, and the pcb rework process. figure 1. 3d view of micro foot products si8902db and si8900edb figure 2. outline of micro foot csp & analog switch dg3000db 0.18 ~ 0.25 321 a b 0.5 1.58 0.5 0.285 0.285 1.08
an824 vishay siliconix www.vishay.com 2 document number: 71990 06-jan-03 table 1 main parameters of solder bumps in micro foot designs micro foot csp mosfet micro foot?s design and reliability as a mechanical, electrical, and thermal connection between the device and pcb, the solder bumps of micro foot products are mounted on the top active surface of the die. table 1 shows the main parameters for solder bumps used in micro foot products. a silicon nitride passivation layer is applied to the active area as the last masking process in fabrication,ensuring that the device passes the pressure pot test. a green laser is used to mark the backside of the die without damaging it. reliability results for micro foot products mounted on a fr-4 board without underfill are shown in table 2. table 2 micro foot reliability results test condition c: ? 65 to 150 c ? 40 to 125 c c @ 15psi 100% humidity test board layout guidelines board materials . vishay siliconix micro foot products are designed to be reliable on most board types, including organic boards such as fr-4 or polyamide boards. the package qualification information is based on the test on 0.5-oz. fr-4 and polyamide boards with nsmd pad design. land patterns. two types of land patterns are used for surface-mount packages. solder mask defined (smd) pads have a solder mask opening smaller than the metal pad (figure 3), whereas on-solder mask defined (nsmd) pads have a metal pad smaller than the solder-mask opening (figure 4). nsmd is recommended for copper etch processes, since it provides a higher level of control compared to smd etch processes. a small-size nsmd pad definition provides more area (both lateral and vertical) for soldering and more room for escape routing on the pcb. by contrast, smd pad definition introduces a stress concentration point near the solder mask on the pcb side that may result in solder joint cracking under extreme fatigue conditions. copper pads should be finished with an organic solderability preservative (osp) coating. for electroplated nickel-immersion gold finish pads, the gold thickness must be less than 0.5 m to avoid solder joint embrittlement. figure 3. smd figure 4. nsmd copper solder mask copper solder mask
an824 vishay siliconix document number: 71990 06-jan-03 www.vishay.com 3 board pad design. the landing-pad size for micro foot products is determined by the bump pitch as shown in table 3. the pad pattern is circular to ensure a symmetric, barrel-shaped solder bump. table 3 dimensions of copper pad and solder mask opening in pcb and stencil aperture pitch copper pad solder mask opening stencil aperture 0.80 mm 0.01 mm 0.01 mm 0.01 mm in ciircle aperture 0.01 mm 0.01 mm 0.01 mm in square aperture assembly process micro foot products? surface-mount-assembly operations include solder paste printing, component placement, and solder reflow as shown in the process flow chart (figure 5). figure 5. smt assembly process flow stencil design iincoming tape and reel inspection solder paste printing chip placement reflow solder joint inspection pack and ship stencil design . stencil design is the key to ensuring maximum solder paste deposition without compromising the assembly yield from solder joint defects (such as bridging and extraneous solder spheres). the stencil aperture is dependent on the copper pad size, the solder mask opening, and the quantity of solder paste. in micro foot products, the stencil is 0.125- mm (5-mils) thick. the recommended apertures are shown in table 3 and are fabricated by laser cut. solder-paste printing. the solder-paste printing process involves transferring solder paste through pre-defined apertures via application of pressure. in micro foot products, the solder paste used is up78 no-clean eutectic 63 sn/37pb type3 or finer solder paste. chip pick-and-placement. micro foot products can be picked and placed with standard pick-and-place equipment. the recommended pick-and-place force is 150 g. though the part will self-center during solder reflow, the maximum placement of fset is 0.02 mm. reflow process . micro foot products can be assembled using standard smt reflow processes. similar to any other package, the thermal profile at specific board locations must be determined. nitrogen purge is recommended during reflow operation. figure 6 shows a typical reflow profile. 0 50 100 150 200 250 0 100 200 300 400 thermal profile time (seconds figure 6. reflow profile temperature ( c) pcb rework to replace micro foot products on pcb, the rework procedure is much like the rework process for a standard bga or csp, as long as the rework process duplicates the original reflow profile. the key steps are as follows: 1. remove the micro foot device using a convection nozzle to create localized heating similar to the original reflow profile. preheat from the bottom. 2. once the nozzle temperature is +190 c, use tweezers to remove the part to be replaced. 3. resurface the pads using a temperature-controlled soldering iron. 4. apply gel flux to the pad. 5. use a vacuum needle pick-up tip to pick up the replacement part, and use a placement jig to placed it accurately. 6. reflow the part using the same convection nozzle, and preheat from the bottom, matching the original reflow profile.
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